The present invention generally relates to the formation of transistor gates, and more specifically relates to the application of a gate edge liner to maintain gate length critical dimension (“CD”) in a gate transistor flow.
The aggressive scaling of MOS devices is quickly reaching the fundamental limits of SiO2 as the gate dielectric. Scaling requirements can no longer be achieved with SiO2 or nitrided-SiO2 as the gate dielectric due to direct tunneling resulting in excessive leakage current and a lack of manufacturability of sub-1 nm oxides. Moreover, poly-Si depletion and threshold voltage shifts due to boron penetration into the channel region severely degrade device performance. Replacement of SiO2-based gate dielectrics with a high dielectric constant (high-k) material provides a means to address scaling issues. A high-k material allows for a physically thicker film to meet the required gate capacitance, while reducing the leakage current due to direct tunneling and improving manufacturability.
It has been shown that high-k materials are susceptible to boron penetration just as SiO2. In order to prevent boron penetration into the channel, capping layers or nitridation of the high-k material have been employed. However, this is done at the price of increasing the equivalent oxide thickness (EOT), i.e. decrease in the gate capacitance. The issue of poly-Si depletion is still not overcome when using a high-k material, since the 3-6 Å contribution to EOT due to poly-Si depletion is still about 30-50% of the target EOT. As a result, the semiconductor industry began investigating metal gate electrodes. Replacement of poly-Si with a metal electrode solves both the boron penetration and poly-Si depletion issues. Moreover, the introduction of metal gates can prolong the use of SiO2 for one or two technology generations for high performance applications before the needed switch to high-k dielectrics.
A major challenge to the introduction of metal electrodes is addressing the issue of how to integrate these materials into conventional transistor processing. In the case of CMOS and partially depleted SOI, two metal types will be needed—one with an n-type work function, and one with a p-type work function. In the case of fully depleted SOI, a single metal with a mid-gap work function can be used. Whether one type or two types of metals are used, the integration question is still open. Many candidate metals will not sustain a standard Source/drain activation anneal due to either reaction with the gate dielectric or the low melting temperature of many metal materials. In order to increase the number of candidate metal materials, a replacement gate approach is very appealing.
The replacement gate approach uses a dummy gate stack to define the source/drain area, thereby maintaining a self-aligned process as achieved with an etched gate approach. There are variations of this scheme, but the essential steps are as follows: sacrificial SiO2 growth and poly-Si deposition (t patterning, resist ashing and stripping (removes sacrificial SiO2 outside the gate areas); LDD masking, implanting, resist ashing and stripping; spacer LTO and SiN deposition, etching; SD implanting annealing; ILD deposition, CMP (chemical mechanical polishing); wet etching of Poly-Si and the sacrificial SiO2 underneath (also removes part of the LTO under the SiN spacer); gate oxide growth (e.g., thermal oxidation, plasma oxidation, high K deposition); metal fill; CMP (chemical mechanical polishing; and ILD and contact fabrication.
So, after source/drain implants, spacer definition and CMP (or etchback) of the inter-layer dielectric (ILD), the dummy gate stack is removed and replaced with the SiO2/metal gate or high-k/metal gate structure. A major challenge for the replacement gate process is to remove the dummy gate stack, typically consisting of poly-Si/SiO2. Removal of the dummy electrode can be achieved via dry or wet etching. Dry etching of the dummy gate dielectric is not a viable option due to damage to the channel region, resulting in severe degradation to the device. Therefore, a wet etch process is needed to remove the dummy gate dielectric. The need for a wet etch process to remove the dummy gate dielectric is the major problem of existing replacement gate schemes. The isotropic nature of a wet etching process leads to under-cut of the LTO underneath the nitride spacer. This leads to the following disadvantages:                a) Lack of gate length control: undercutting of LTO under the SiN spacer changes the original gate length CD defined by the dummy gate.        b) Lack of gate dielectric thickness uniformity: the undercutting also results in the non-uniformity of the high-K dielectric in the final transistor. This non-uniformity affects the electric field distributions in the dielectric as well as in the channel, causing degradation in channel mobility and dielectric reliability.        